I. Field of the Disclosure
The technology of the disclosure relates generally to memory systems in integrated circuits.
II. Background
Mobile communication devices have become common in current society. The prevalence of these mobile devices is driven in part by the many functions that are now enabled on such devices. Demand for such functions increases processing capability requirements and generates a need for more powerful batteries. Within the limited space of the housing of the mobile communication device, batteries compete with the processing circuitry. The limited space contributes pressure to a continued miniaturization of components and control of power consumption within the circuitry. While miniaturization has been of particular concern in the integrated circuits (ICs) of mobile communication devices, efforts at miniaturization of ICs in other devices also occur.
While miniaturization efforts have progressed in general compliance with Moore's Law, the space savings achieved by shrinking the active components are almost immediately offset by IC designs that add additional active elements to provide increased functionality. In conventional two dimensional (2D) designs, active elements within an IC have all been placed in a single active layer with elements interconnected through one or more metal layers that are also within the IC. As the number of active elements within an IC increases, the routing requirements to effectuate desired interconnections between elements become increasingly complex.
The difficulty in routing interconnections is particularly acute within the memory elements. That is, while smaller memory bit cells do allow component miniaturization, increased functionality requires more available memory and accordingly, more and more memory bit cells are assembled into memory banks for each device. As the number of memory bit cells within a memory bank increases, the access lines (such as the bit line (BL) or word line (WL)) for such bit cells become increasingly long. As the length of the access lines becomes longer, the difficulty in routing the lines increases. Normally, memory banks may make use of a fully-static complementary metal oxide semiconductor (CMOS) fabric switch consisting on inter-block routes, multiplexers and repeaters for client-to-client interaction. The use of such a fabric switch allows the memory pools to save metal route congestion. Even with such fabric switches, memory pools require crossbars (sometimes referred to as “xBar”) as inter-block communication channels in 2D designs. These crossbars take up significant routing resources that compete with top-level routes. Additionally, these crossbars are typically millimeter(s) long. Such lengths necessitate the use of repeaters, and have significant resistive-capacitive (RC) delay associated with them, limiting the memory access (or inter-block communication) time.